The fabrication of integrated circuits often involves one or more steps of electroplating a layer of conductive metal onto the surface of a semiconductor wafer. For example, in some IC fabrication procedures, an electroplating operation may be used to fill with metal the various features formed in the surface of a semiconductor wafer such as, for instance, the trenches and vias used as conductive paths between various circuit elements.
In a typical electroplating operation, the surface of the wafer is exposed to an electroplating bath fluid which contains dissolved ions of the metal to be electroplated, and an electrical circuit is created between an electrode in the bath (which serves as an anode) and surface of the wafer (which serves as the cathode). Flow of current through this circuit upon application of an applied electrical potential difference causes electrons to flow to the cathodic wafer surface and reduce dissolved metal ions in its vicinity thereby resulting in the plating out of solution of neutral elemental metal onto the surface of the wafer.
However, for this circuit to be completed and for electrochemical reduction of dissolved metal ions to occur, the surface of the wafer (serving as the circuit's cathode) must be, at least to a certain extent, relatively conductive. Accordingly, since the bare surface of a semiconductor wafer is not generally substantially conductive, the actual electroplating step in an electroplating operation (sometimes referred to as “electrofill”) is often preceded by the deposition of a conductive seed layer (typically quite thin) which initially provides the necessary conductive surface. Deposition of the seed layer may be accomplished by any feasible method of depositing the seed material. Suitable methods may include, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), conformal film deposition (CFD), atomic layer deposition (ALD), and the like. Oftentimes, the seed layer is separated from an insulating silicon dioxide layer or other dielectric by a barrier layer. Furthermore, oftentimes, seed layer deposition and electroplating is followed by an edge bevel removal (EBR) operation that removes seed metal deposited at the edge of the wafer where its presence is not desired.
As the semiconductor industry advances, future technology regimes are likely to require extremely thin and resistive seed layers for electroplating operations. High-resistance seed layers cause it to be much more challenging to achieve a uniform electroplating thickness/current across the wafer surface because, when very resistive seed layers are used, the potential at the edge of the wafer—i.e., at the point of electrical contact—is much greater than in the center of the wafer—further away from the electrical contact. This center to edge variation in electrical potential can lead to significantly thicker plating at the edge of the wafer versus its center, a phenomenon oftentimes referred to as the “terminal effect.” The effect is undesirable, of course, because it reduces usable wafer surface area in the edge region. Future use of larger-diameter wafers may further exacerbate the problem. Thus, effective methods and apparatuses are needed for controlling ionic current during electroplating so as to better control the thickness of the metal deposited at the edge of semiconductor substrates in electroplating operations.